Memory controller and method for operating a memory controller having an integrated bit error rate circuit
US7853837B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2007 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Feb 26, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3171
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, among other embodiments, includes a memory controller having an integrated BER circuit and a plurality of memory devices. The memory controller also includes a control circuit and an interface having at least one transmit circuit to provide write data to at least one of the memory devices and at least one receive circuit to receive read data from at least one of the memory devices. The BER circuit includes a request generator circuit that outputs a request for a memory transaction. A request multiplexer selectively outputs a memory request to the interface from the request generator circuit or the control circuit. A data generator circuit outputs corresponding write data. A first write multiplexer selectively outputs the write data to the interface from the data generator circuit or the control circuit. A read multiplexer selectively receives read data from the receive circuit. The data generator circuit also outputs corresponding write data to a comparator circuit via a second write multiplexer. The comparator circuit outputs an error signal in response to a comparison of the received read data and corresponding stored write data. A counter outputs a count value indicati…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.