Method and apparatus for preserving the context of tasks during task switching in a pipeline architecture
US7853954B2 · kind B2 · utility
3Cited by
6References
2Claims
0Family size
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Key dates
| Filing date | Jul 7, 2005 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Oct 13, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/485
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor executes programs in a pipeline architecture including a task register management unit that, if a switch instruction to a second task is issued when a plurality of units executes a first task, switches a value of a task register to second register information that is used when the second task is executed after the execution of the first task is completed and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.