Method for manufacturing integrated circuits by guardbanding die regions
US7855088B2 · kind B2 · utility
4Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2006 |
| Grant date | Dec 21, 2010 |
| Priority date | — |
| Expiry date | Apr 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a method for manufacturing an integrated circuit. The method, in one embodiment, includes inspecting a semiconductor wafer including a plurality of die for a defect, the inspecting providing an image of the semiconductor wafer including the defect. The method further includes identifying an area of the semiconductor wafer from the image, wherein the identified area encompasses at least those die including any portion of the defect, and dicing the semiconductor wafer into individual die. The die defined by the identified area, in this embodiment, are then discarded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.