Method of increasing yield in OFETs by using a high-K dielectric layer in a dual dielectric layer
US7855097B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 2008 |
| Grant date | Dec 21, 2010 |
| Priority date | — |
| Expiry date | Feb 12, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K10/476
Abstract
Dielectric layer pinholes in OFET structures are addressed in a method of fabricating OFET devices through the addition of a high-K dielectric layer to eliminate the effects of shorts in the dielectric layer. The original dielectric layer is maintained such that the semiconductor/dielectric interface remains unchanged. The high-K dielectric layer contributes material to the gate dielectric to plug up pinholes in the original dielectric, but does not contribute significant capacitance due to the high dielectric constant of the additional dielectric layer. The incidence of pinholes in the dielectric layer is reduced without significantly affecting the performance of the OFET transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.