Data processing memory circuit having pull-down circuit with on/off configuration
US7855924B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2006 |
| Grant date | Dec 21, 2010 |
| Priority date | — |
| Expiry date | Oct 21, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a memory cell, a pair of conducting lines operable to signal the logic state of the memory cell and read circuitry operable to perform a read operation by detecting a voltage level of at least one of the pair of conducting lines. The memory circuit includes a pull-down circuit having an on configuration in which it is operable to pull-down a voltage level of at least one of the pair of conducting lines so as to affect the read operation and an off-configuration in which the pull-down circuit cannot affect the read operation. Control circuitry is configured to control whether the pull-down circuit is in the on configuration or the off configuration. The memory circuit can be incorporated in a data processing apparatus and a method of operating a memory circuit is provided in which a pull-down circuit is controlled to be in an on configuration or in an off configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.