Power dissipation management for wired transceivers
US7856028B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2006 |
| Grant date | Dec 21, 2010 |
| Priority date | — |
| Expiry date | Jun 13, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system, method and apparatus for reducing a power consumed by a physical layer device (PHY). A length of a cable connecting the PHY to a link partner is determined. Based on the length, power provided to one or more components of the PHY, or any portion thereof, is reduced. The power provided is reduced while maintaining a level of reliability specified by a protocol governing operation of the PHY. The length can be determined using time-domain reflectometry (TDR) techniques. Any portion of an echo cancellation filter, a crosstalk filter, an equalizer, a precoder, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a forward error correction (FEC) decoder and/or an FEC coder can be powered-down or power-optimized to reduce the overall power consumed by the PHY. The protocol governing operation of the PHY can be IEEE 802.3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.