Cache logic, data processing apparatus including cache logic, and a method of operating cache logic
US7856532B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2006 |
| Grant date | Dec 21, 2010 |
| Priority date | — |
| Expiry date | Dec 5, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cache logic is provided for use in a data processing apparatus, the cache logic having a cache storage comprising a plurality of cache lines for storing data values. Control logic is arranged, in response to an access request issued by a device of the data processing apparatus identifying a memory address of the data value to be accessed, to cause a lookup operation to be performed to determine whether the data value for that memory address is stored within the cache storage. The control logic is further operable if the data value is not stored in the cache storage to perform a linefill process, the linefill process comprising performing an eviction to evict to memory of the data processing apparatus current content of a selected cache line, keeping the current content valid in the selected cache line whilst the eviction is taking place, and storing from the memory into the selected cache line new content including the data value the subject of the access request. Whilst the eviction is taking place, the control logic allows the current content of the selected cache line to be accessed by subsequent read access requests seeking to read a data value within that current content, but …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.