Data processing architectures for packet handling wherein batches of data packets of unpredictable size are distributed across processing elements arranged in a SIMD array operable to process different respective packet protocols at once while executing a single common instruction stream
US7856543B2 · kind B2 · utility
7Cited by
32References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2002 |
| Grant date | Dec 21, 2010 |
| Priority date | — |
| Expiry date | Apr 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/742
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data processing architecture comprising:
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.