Method and system for managing memory transactions for memory repair
US7856576B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2007 |
| Grant date | Dec 21, 2010 |
| Priority date | — |
| Expiry date | Sep 24, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/883
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a controller for an associative memory having n ways contains circuitry for sending a request to search an indexed location in each of the n ways for a tag, wherein the tag and an index that is used to denote the indexed location form a memory address. The controller also contains circuitry, responsive to the request, for sending a set of n validity values, each validity value indicating, for a respective way, whether the indexed location is a valid location or a defective location. Additionally, the controller contains circuitry for receiving a hit signal that indicates whether a match to the tag was found at any of the indexed locations, wherein no hit is ever received for a defective location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.