Semiconductor device having dual-STI and manufacturing method thereof
US7858490B2 · kind B2 · utility
7Cited by
3References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2008 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | Jun 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/44
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.