Fabrication of self-aligned via holes in polymer thin films
US7858513B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2007 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | Jul 12, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K71/40
Abstract
A low-cost and efficient process produces self-aligned vias in dielectric polymer films that provides electrical connection between a top conductor and a bottom conductor. The process is achieved by printing conductive posts on the first patterned conductive layer, followed by the deposition of an unpatterned layer dielectric, followed by the deposition of a second patterned conductive layer. The vias are formed during the flash annealing of the post after the dielectric is deposited, but before the second conductive layer is deposited. In this process, the post material is annealed with a flash of light, resulting in a release of energy which removes the dielectric on the top of the post.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.