Integrated circuit and manufacturing method of copper germanide and copper silicide as copper capping layer
US7858519B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 3, 2008 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | Jul 8, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming a capping layer comprising Cu, N, and also Si and/or Ge onto a copper conductive structure, said method comprising the sequential steps of: forming, at a temperature range between 200° C. up to 400° C., at least one capping layer onto said copper conductive structure by exposing said structure to a GeH4 and/or a SiH4 comprising ambient, performing a NH3 plasma treatment thereby forming an at least partly nitrided capping layer, forming a dielectric barrier layer onto said at least partly nitrided capping layer, wherein prior to said step of forming said at least one capping layer a pre-annealing step of said copper conductive structure is performed at a temperature range between 250° C. up to 450° C.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.