Power regulator circuitry for programmable logic device memory elements
US7859301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2007 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | Mar 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17792
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Power regulator circuitry for programmable memory elements on programmable logic device integrated circuits is provided. The programmable memory elements may each include a storage element formed from cross-coupled inverters and an address transistor. Address drivers may be used to supply address signals to the address transistors. The power regulator circuitry may include an address power supply circuit that produces a time-varying address power supply voltage to the address drivers and storage element power supply circuits that provide time-varying storage element power supply voltages to the cross-coupled inverters in the storage elements. Unity gain buffers may be used to distribute a reference voltage from a bandgap voltage reference to the power supply circuits. The power supply circuits may use voltage dividers and p-channel metal-oxide-semiconductor control transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.