Anti-fuse latch self-test circuit and method
US7859925B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 21, 2007 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | Aug 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable latch circuit (200) can include a volatile latch (206) that may regenerate a value determined by programmable section (202). In a test operation, a variable current source (216′) can generate a current (IBASE) that can be mirrored in test sections (252-0 and 252-1) and compared to a current drawn by either programmable element (210-0) or (210-1) by a latching operation of volatile latch (206). Variable current source (216′) can enable characterization of programmable elements (210-0 or 210-1) as well as adjustable test threshold limits. A program voltage (Vprog) applied to programmable elements (210-0 or 210-1) can be also be variable to allow for characterization of programmable elements (210-0 and 210-1) over a range of voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.