Semiconductor memory device
US7859926B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 3, 2009 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | May 13, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor memory device including a discharge circuit that discharges bit lines to a ground potential, a sense amplifier of a single-ended input configuration, and a charging transistor connected between a power supply and an input node of the sense amplifier. The charging transistor charges a bit line from a side of the input node of the sense amplifier via the selected column select transistor which is set to an on state. When a current path to the ground from the bit line to which a selected memory cell is connected is turned off at a time of reading, the input node of the sense amplifier is charged by the charging transistor, and a potential at the input node of the sense amplifier is thereby raised. Then, after the input node of the sense amplifier has been further charged with the one of the column select transistors turned off, the reading operation is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.