Clock synchronization using a weighted least squares error filtering technique
US7860205B1 · kind B1 · utility
48Cited by
5References
21Claims
0Family size
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Key dates
| Filing date | Apr 12, 2006 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | Sep 24, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/8547
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A timestamp-based clock synchronization technique is employed for CES in packet networks. The technique is based on a double exponential filtering technique and a linear process model. The linear process model is used to describe the behavior of clock synchronization errors between a transmitter and a receiver. The technique is particularly suitable for clock synchronization in networks where the transmitter and receiver are not driven from a common timing reference but the receiver requires timing reference traceable to the transmitter clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.