Patent · US Active

Clock data recovery (CDR) system using interpolator and timing loop module

US7861105B2 · kind B2 · utility

2Cited by

18References

11Claims

0Family size

Assignee

Analogix Semiconductor, Inc. · US

Inventors

Yanjing Ke · Union City, US
Jianbin Hao · San Jose, US
Ning Zhu · 安丰镇, CN

Key dates

Filing date	Jun 25, 2007
Grant date	Dec 28, 2010
Priority date	—
Expiry date	Jul 12, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH04L7/0008
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

The present invention provides a method and mechanism for data recovery with phase synchronized clock using interpolator and timing loop module and a data latching circuit. The interpolator can be considered as a programmable delay circuit with a specified delay resolution over the clock period.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.