Combined micro-electro-mechanical systems device and integrated circuit on a silicon-on-insulator wafer
US7863071B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2007 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | May 17, 2028 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C1/00246
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The present invention includes a fabrication method to construct a combined MEMS device and IC on a silicon-on-insulator (SOI) wafer (MEMS-IC) using standard foundry IC processing techniques. The invention also includes the resulting MEMS-IC. Deposition layers are added to the SOI wafer and etched away to form interconnects for electronic components for the IC. In one embodiment of the present invention, standard foundry IC processing etching techniques may be used to etch away parts of the insulating layer and device layer of the SOI wafer to create fine gaps and other detailed mechanical features of the MEMS device. Finely detailed etching patterns may be added by using imprint lithography instead of using contact or optical lithography.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.