Thin film transistor array panel and manufacturing method thereof
US7863607B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2007 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Dec 1, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
The disclosed thin film transistor array panel includes an insulating substrate, a channel layer including an oxide formed on the insulating substrate. A gate insulating is layer formed on the channel layer and a gate electrode is formed on the gate insulating layer. An interlayer insulating layer is formed on the gate electrode and a data line formed on the interlayer insulating layer and includes a source electrode, wherein the data line is made of a first conductive layer and a second conductive layer. A drain electrode formed on the interlayer insulating layer, and includes the first conductive layer and the second conductive layer. A pixel electrode extends from the first conductive layer of the drain electrode and a passivation layer formed on the data line and the drain electrode. A spacer formed on the passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.