MEMS device with integrated via and spacer
US7863752B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 25, 2009 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Mar 19, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49002
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A MEMS device and fabrication method are disclosed. A bottom substrate having an insulating layer sandwiched between an upper layer and a lower layer may be bonded to a device layer. One or more portions of the upper layer may be selectively removed to form one or more device cavities. Conductive vias may be formed through the lower layer at locations that underlie the one or more device cavities and electrically isolated from the lower layer. Devices may be formed from the device layer. Each device overlies a corresponding device cavity. Each device may be connected to the rest of the device layer by one or more corresponding hinges formed from the device layer. One or more electrical contacts may be formed on a back side of the lower layer. Each contact is electrically connected to a corresponding conductive via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.