High frequency amplifier linearization technique
US7863985B1 · kind B1 · utility
1Cited by
7References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2009 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Jul 29, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/91
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output stage for an amplifier is provided. The amplifier generally provides for compensation of an error current generated by the base-collector (or gate-drain) capacitance of a common base (or gate) amplifier transistor. The stage accomplishes this by utilizing a three transistor Wilson current mirror to combine the error current with a mirrored bias current to reduce the load current on the common base (or gate) amplifier transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.