Display panel
US7864149B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2007 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Mar 31, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2300/0876
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
In a display panel, main and sub pixel electrodes are connected to first and second drain electrodes of a thin film transistor, respectively, to receive a data voltage during a 1 H period as main and sub pixel voltages. A main storage electrode overlaps the main pixel electrode to receive a first common voltage that varies with the gate pulse and the polarity of the data voltage. A sub storage electrode overlaps the sub pixel electrode to receive a second common voltage that is uniformly maintained at a constant voltage level. The sub pixel voltage is uniformly maintained by the second common voltage, but the main pixel voltage is shifted up or down by the first common voltage. Thus, the main pixel voltage may have a voltage level higher than that of the sub pixel voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.