Capacitors with low equivalent series resistance
US7864507B2 · kind B2 · utility
11Cited by
90References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2007 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | May 16, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E60/13
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An electric double layer capacitor (EDLC) in a coin or button cell configuration having low equivalent series resistance (ESR). The capacitor comprises mesh or other porous metal that is attached via conducting adhesive to one or both the current collectors. The mesh is embedded into the surface of the adjacent electrode, thereby reducing the interfacial resistance between the electrode and the current collector, thus reducing the ESR of the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.