Memory module decoder
US7864627B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2009 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Oct 12, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The plurality of memory devices has a first number of memory devices. The circuit comprises a logic element configurable to receive a set of input signals from the computer system. The circuit further comprising a register and a phase-lock loop circuit, the phase-lock loop circuit configurable to be operatively coupled to the plurality of memory devices, the logic element, and the register. The set of input signals corresponds to a second number of memory devices smaller than the first number of memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.