Memory load balancing

US7865037B1 · kind B1 · utility

Assignee

• KLA-TENCOR CORPORATION · US

Inventors

• Krishnamurthy Bhaskar · San Jose, US
• Mark J. Roulo · Milpitas, US
• John S. Taylor · San Jose, US
• Lawrence R. Miller · New York, US
• Paul T. Russell · Scotts Valley, US
• Jason Z. Lin · Saratoga, US
• Eliezer Rosengaus · Palo Alto, US
• Richard Wallingford · San Jose, US
• Kishore Bubna · Fremont, US

Key dates

• Filing date: May 16, 2006
• Grant date: Jan 4, 2011
• Expiry date: Sep 22, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T7/0004
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An inspection system for detecting anomalies on a substrate. A first network is coupled to a sensor array and communicates data. Process nodes are coupled to the first network, and process the data to produce reports. Each process node includes memory sufficient to buffer the data until it can process the data. Each process node has an interface card that formats the data for a high speed interface bus that is coupled to the interface card. A computer receives and processes the data to produce the report. A second network receives the reports. A job manager is coupled to the second network, receives the reports, and sends information to the process nodes to coordinate processing of the data.