Adaptive issue queue for reduced power at high performance
US7865747B2 · kind B2 · utility
8Cited by
11References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2001 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Mar 1, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and structure of reducing power consumption in a microprocessor includes at least one storage structure in which the activity of the storage structure is dynamically measured and the size of the structure is controlled based on the activity. The storage structure includes a plurality of blocks, and the size of the structure is controlled in units of block size, based on activity measured in the blocks. An exemplary embodiment is an adaptive out-of-order queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.