Fault tolerant time synchronization mechanism in a scaleable multi-processor computer

US7865758B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Scott Barnett Swaney · Catskill, US
• Kenneth L. Ward · Austin, US
• Tobias Webel · Eppelheim, DE
• Ulrich Weiss · Holzgerlingen, DE
• Matthias Woehrle · Bietigheim-Bissingen, DE

Key dates

• Filing date: Jun 16, 2008
• Grant date: Jan 4, 2011
• Expiry date: Nov 6, 2028

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/20
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.