System and method for improved visualization and debugging of constraint circuit objects
US7865857B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2007 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Nov 8, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Features are provided for graphically representing constraints on design objects in an Electronic Design Automation tool. A particular constraint on one or more circuit objects is displayed as a highlighted region that extends to each visible circuit object to which the constraint applies. Attributes of the highlighted region, such as density and thickness, may proportionally represent attributes of the constraint, such as a strength or distance specified by the constraint. The highlighted region is superimposed on or around circuit objects. The highlighted region may be a halo, which is a partially transparent region filled with a color. Multiple regions that represent the same type of constraint or relationship are connected by line segments, providing the ability to visualize groups of constrained objects, including groups that span levels of a hierarchical design. Intersecting highlighted regions are blended together using techniques such as alpha blending.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.