Methods and apparatus for LDMOS transistors

US7868378B1 · kind B1 · utility

Assignee

• VOLTERRA SEMICONDUCTOR LLC · US

Inventors

• Marco A. Zuniga · Berkeley, US
• Budong You · Hangzhou City, CN
• Yang Lu · Boise, US

Key dates

• Filing date: Jul 17, 2006
• Grant date: Jan 11, 2011
• Expiry date: Aug 8, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0285

Abstract

An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.