Low-quiescent-current buffer
US7868666B2 · kind B2 · utility
3Cited by
12References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2009 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | Apr 8, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An embodiment of an input-buffer circuit may include an input stage with an inverter having an input operable to receive a signal to be translated. The input stage may include a limiting circuit coupled to the input stage for arresting quiescent current. Additional embodiments of an input-buffer circuit formed according to the subject matter disclosed herein may include feedback transistors suited to provide additional current to the input stage and a hysteresis circuit suited to provide hysteresis current to the input stage when an input signal has a high-frequency change rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.