Patent · US Active

Phase-locked loop (PLL) circuit and method

US7868670B2 · kind B2 · utility

2Cited by

6References

3Claims

0Family size

Assignee

TEXAS INSTRUMENTS DEUTSCHLAND GMBH · DE

Inventors

Georg Becke · Moosburg an der Isar, DE
Gerd Rombach · Freising, DE

Key dates

Filing date	Aug 20, 2007
Grant date	Jan 11, 2011
Priority date	—
Expiry date	Dec 7, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/0891
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A phase-locked loop (PLL) circuit includes a reference clock divider with a reference clock input, a phase-frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a feedback divider. A method of operating the PLL circuit comprises the steps of detecting a failure of a reference clock applied to the reference clock input, disabling the charge pump upon detection of a reference clock failure, monitoring the reference clock to detect restoration of a regular reference clock, upon detection of a regular reference clock, detecting occurrence of the next pulse from the feedback divider, and enabling the charge pump upon detection of the next pulse from the feedback divider.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.