Digital phase-locked loop with two-point modulation and adaptive delay matching
US7868672B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2008 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | Dec 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03C3/0966
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase-locked loop (DPLL) supporting two-point modulation with adaptive delay matching is described. The DPLL includes highpass and lowpass modulation paths that support wideband and narrowband modulation, respectively, of the frequency and/or phase of an oscillator. The DPLL can adaptively adjust the delay of one modulation path to match the delay of the other modulation path. In one design, the DPLL includes an adaptive delay unit that provides a variable delay for one of the two modulation paths. Within the adaptive delay unit, a delay computation unit determines the variable delay based on a modulating signal applied to the two modulation paths and a phase error signal in the DPLL. An interpolator provides a fractional portion of the variable delay, and a programmable delay unit provides an integer portion of the variable delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.