Low power flip-flop circuit
US7868677B2 · kind B2 · utility
19Cited by
5References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2007 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | Feb 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop circuit having low power consumption includes a sensing circuit, and a clock generating circuit. The flip-flop is leading edge triggered and operates on an internally generated pseudo clock signal. The sensing circuit senses a change in an input signal and an output signal of the flip-flop. The clock generating circuit generates a pseudo clock signal with a sharp rise and fall based upon an external clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.