Comparator with sensitivity control
US7868690B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 27, 2008 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | Jul 11, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D1/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparator has a differential input stage, a current source coupled to the differential input stage for providing a tail current to one side of the differential input stage, and a differential load coupled to the differential pair and having at least one diode coupled load transistor per differential side. A load current through either one of the at least one diode coupled load transistor on either differential side is mirrored with a current mirror configuration to provide a current be fed to a respective node, each node being coupled to a respective variable biasing current source and a respective other side of the differential input stage, so as to provide a variable positive feedback to the differential input stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.