Semiconductor memory which enables reliable data writing with low supply voltage by improving the conductance via access transistors during write operation
US7869261B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 4, 2006 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | Apr 4, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory maintains securely the stored contents in the memory cells, and it is written with data reliably even in a case where a relatively low supply voltage is applied. A memory cell M00 comprises a pair of inverters cross-coupled with each other, a first switching unit provided between bit line BL and the output terminal of one of the inverters, and a second switching unit provided between bit line XBL and the output terminal of the other inverter. The first switching unit and the second switching unit are controlled to be conductive such that the conductance of the switches be larger for the writing operation than for the reading operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.