Patent · US Active

Network receive interface for high bandwidth hardware-accelerated packet processing

US7869355B2 · kind B2 · utility

33Cited by
15References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 1, 2008
Grant dateJan 11, 2011
Priority date
Expiry dateDec 1, 2028

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH04L69/12
  • WIPO fieldDigital communication
  • WIPO sectorElectrical engineering

Abstract

Disclosed is a system and methods for accelerating network packet processing for devices configured to process network traffic at relatively high data rates. The system incorporates a hardware-accelerated packet processing module that handles in-sequence network packets and a software-based processing module that handles out-of-sequence and exception case network packets.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.