Power-aware line intervention for a multiprocessor snoop coherency protocol
US7870337B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2007 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | Mar 12, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A snoop coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.