Patent · US Active

Transitioning to and from a sleep state of a processor

US7870404B2 · kind B2 · utility

4Cited by

96References

21Claims

0Family size

Inventors

Andrew Read · Volbringen, DE
Sameer Halepete · San Jose, US
Keith Klayman · Sunnyvale, US

Key dates

Filing date	Aug 21, 2007
Grant date	Jan 11, 2011
Priority date	—
Expiry date	Sep 2, 2028

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for reducing power utilized by a processor including determining that a processor is transitioning from a computer mode to a mode in which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.