Clock processors in high-speed signal converter systems with data clock aligner sharing error signal produced in duty cycle stabilizer
US7870415B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2007 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | Sep 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Clock processors are provided to economically control system and data clocks in high-speed signal converters. The processors generally include at least one of a delay-locked loop, phase-locked loop or a duty cycle stabilizer which generates an error signal in its operation. In the example of a stabilizer, it is configured to respond to an input clock to initiate a first portion of each cycle of the system clock and to include a control loop to provide an error signal that controls a second portion of the cycle to thereby maintain a selected duty cycle. The processors also include a data clock aligner configured to share the error signal and provide a data clock that is delayed by a selected delay from a selected one of the input and system clocks. In addition to providing effective control that is independent of disturbing effects (e.g., temperature and clock rate), the shared use reduces processor costs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.