Parallel arrangement of serial concatenated convolutional code decoders with optimized organization of data for efficient use of memory resources
US7870458B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2007 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | Sep 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6561
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decoding system (100) is provided. The decoding system is comprised of two or more serial concatenated convolutional code (SCCC) decoders (1021-102N) operating in parallel. The SCCC decoders are configured to concurrently decode codeblocks which have been encoded using a convolutational code. The decoding system is also comprised of a single common address generator (108) and data store (114). The address generator is responsive to requests for data needed by two or more of the SCCC decoders for permutation and depermutation. The data store is comprised of two or more memory blocks (1161-116K). The SCCC decoders concurrently generate requests for two or more different data types. Selected ones of the different data types are exclusively stored in different ones of the memory blocks. Selected ones of the different data types are comprised of data which is requested at the same time by a particular one of the SCCC decoders.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.