Method for connecting flip chip components
US7871831B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2006 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Dec 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An automated system and method for determining flip chip connections involves generating a first projection that includes representations of bumps arranged over a core of the flip chip and generating a second projection that includes representations of I/O pads arranged around the core. The first projection is generated by drawing a line through each bump between a location of the flip chip and an outer portion of the flip chip and marking a location where the line terminates at the outer portion with a representation of the bump. The outer portion of the flip chip is traversed, and the first projection is generated based on the order in which bump representations are encountered. The second projection is generated by drawing a line through each I/O pad between a location of the flip chip and an outer portion of the flip chip and marking a location where the line terminates at the outer portion with a representation of the I/O pad. The outer portion of the flip chip is traversed, and the second projection is generated based on the order in which I/O pad representations are encountered. Connections between bump and I/O representations are made and connecting between bumps and I/O pa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.