Latch circuit and clock signal dividing circuit
US7872514B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2008 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Dec 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Latch circuit and clock signal dividing circuit comprises sequentially connected latch circuits. Each latch circuit has D-type latch with latch clock input, data input and data output. A difference detector is coupled to D-type latch, and has a difference output that provides a difference signal when data at input is different than data at output. Each latch circuit has an edge triggered gate that has gate clock input, output coupled to latch clock input and gate control input coupled to difference output of difference detector. In operation, when both a transition of clock signal supplied at gate clock input is detected by edge triggered gate, and the difference signal is provided to gate control input, will edge triggered gate allow an edge of a clock signal supplied at gate clock input to determine logic values supplied to latch clock input. As a result, data at input is transferred to output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.