Bus circuit
US7872517B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2010 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Mar 22, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Clock control is handed over in a bus circuit from a first circuit (14) to a second circuit (12). A clock conductor (10a) is driven to a predetermined voltage level with the driver circuit of the first circuit after a last clock period following the start of execution of the handover command and to continue driving the clock conductor (10a) to the predetermined voltage level for a first time-interval. The clock conductor (10a) is driven to the predetermined voltage level with the driver circuit of the second circuit after a second time interval following the start of execution of the handover command until a third time interval has elapsed following the end of the second time interval. Subsequently the clock conductor (10a) is driven under control of the clock circuit (140) of the second circuit (14). The first time interval contains a first integer number P1 of periods of a first clock signal of the first circuit and the second and third time interval contain a second and third integer number P2, P3 of periods of a second clock signal of the second circuit, a duration corresponding to the second integer number P2 equaling at least a pulse duration of the first clock signal, a dura…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.