Patent · US Active

Integrated circuit with bit lines positioned in different planes

US7872902B2 · kind B2 · utility

1Cited by

6References

20Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Joerg Volrath · Olching, DE
Marcin Gnat · Birkenfeld, DE

Key dates

Filing date	Aug 18, 2008
Grant date	Jan 18, 2011
Priority date	—
Expiry date	Feb 12, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH10D89/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit includes a memory cell array including a plurality of memory cells. A first plurality of bit lines is positioned in a first plane. The first plurality of bit lines is electrically coupled to a first set of the memory cells. A second plurality of bit lines is positioned in a second plane that is different than the first plane. The second plurality of bit lines is electrically coupled to a second set of the memory cells.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.