Memory device and memory data read method
US7872909B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2008 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Jan 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are memory devices and memory data read methods. A method device may include: a multi-bit cell array; a decision unit that may detect threshold voltages of multi-bit cells of the multi-bit cell array to decide first data from the detected threshold voltages, using a first decision value; an error detector that may detect an error bit of the first data; and a determination unit that may determine whether the decision unit decides second data from the detected threshold voltages using a second decision value, based on a number of detected error bits, the second decision value being different from the first decision value. Through this, it is possible to reduce time spent for reading data stored in the multi-bit cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.