Patent · US Active

Testing a memory device having field effect transistors subject to threshold voltage shifts caused by bias temperature instability

US7872930B2 · kind B2 · utility

7Cited by

8References

23Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Nan Chen · San Diego, US
Sian-Yee Sean Lee · Vista, US
Seong-Ook Jung · Seoul, KR
Zhongze Wang · San Diego, US

Key dates

Filing date	May 15, 2008
Grant date	Jan 18, 2011
Priority date	—
Expiry date	Aug 31, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/41
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A supply voltage is set for a memory device at a first supply voltage level. Test data is written to the memory device at the first supply voltage level in response to setting the supply voltage. The supply voltage is decreased for the memory device to a second supply voltage level below the first supply voltage level in response to writing the test data. The test data is read from the memory device at the second supply voltage level in response to decreasing the supply voltage. The supply voltage is increased for the memory device to a third supply voltage level above the second supply voltage level in response to reading the test data. The test data is read from the memory device at the third supply voltage level in response to increasing the supply voltage. The test data written to the memory device at the first supply voltage level is compared to the test data read from the memory device at the third supply voltage level in response to reading the test data from the memory device at the third supply voltage level.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.