Patent · US Active

Method for calculating a result of a division with a floating point unit with fused multiply-add

US7873687B2 · kind B2 · utility

1Cited by

2References

5Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Guenter Gerwig · Simmozheim, DE
Holger Wetter · Holzgerlingen, DE

Key dates

Filing date	Jul 19, 2006
Grant date	Jan 18, 2011
Priority date	—
Expiry date	May 10, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F7/5443
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The invention proposes a Floating Point Unit with fused multiply-add, with one addend Method for calculating a result of a division with an A-register and a B-register for two multiplicand operands and a C-register for an addend operand, wherein a divide processor using a subtractive method for calculation with a divisor register and a partial remainder register and a multiplier associated to an subtractor uses the C-register as input, wherein while loading the fraction of the dividend through the divisor register into the partial remainder register of the divide processor a calculated shifting is applied for alignment by using the multiplier associated to the subtractor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.