Memory controller
US7873797B2 · kind B2 · utility
1Cited by
11References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2004 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Dec 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a memory controller for an IC with an external DRAM, where the external DRAM has at least one memory bank and communicates with the IC via at least one channel. In line with the invention, the memory controller has a command scheduler which prioritizes the transmission of memory bank commands on the basis of a static priority allocation for commands and a dynamic priority allocation for channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.