Address generator for an interleaver memory and a deinterleaver memory
US7873800B2 · kind B2 · utility
1Cited by
5References
50Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 3, 2005 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Sep 4, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/276
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Method and device for generating an address value for addressing an interleaver memory. Consecutive address fragments to which a most significant bit(s) is to be appended are generated. Only a fraction of the address fragments generated, which potentially will exceed a maximum allowable value, is compared to the maximum allowable value. If the compared address fragment exceeds the maximum allowable value it is discarded. If the compared address fragment does not exceed the maximum allowable value it is accepted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.