Method and apparatus for implementing carry chains on field programmable gate array devices
US7873934B1 · kind B1 · utility
6Cited by
6References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 23, 2007 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Feb 13, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system to be implemented on a field programmable gate array (FPGA) includes identifying an adder from an intermediate representation of the system. Components on the target device are designated to support and implement the adder as a partitioned adder having a plurality of sub-adders each registering an intermediate result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.